Palavra-chave: RISC-V

BINARY TRANSLATION ASSEMBLY PROGRAMMING HARDWARE SIMULATION EMULATION OPTIMIZATION FPGA ASIC ARQUITETURA DE COMPUTADORES SOFT-CORE ACELERADORES COMPUTER ARCHITECTURE EDUCATION ASSEMBLY OPENISA COMPUTER ARCHITECTURE MEMORY HIERARCHY LLVM ASSEMBLY LANGUAGE PERFORMANCE EVALUATION PROCESSOR EMULATION PERFORMANCE SIMULAÇÃO DE HARDWARE MATRIX ACCELERATION